1. Field of the Invention
The present invention relates to a method of manufacturing an electronic component package including a plurality of layer portions.
2. Description of the Related Art
A reduction in weight and an improvement in performance have been desired for mobile apparatuses represented by cellular phones and notebook personal computers. Higher integration of electronic components used for mobile apparatuses have been sought, accordingly.
A system large-scale integrated circuit (LSI) and a multi-chip module have been known as highly integrated electronic components. The system LSI is a single integrated circuit (IC) in which functions of various electronic components are incorporated. The multi-chip module is a module made up of a plurality of chips integrated through the use of a wiring board, for example.
The system LSI has a benefit of enabling higher integration density and minimizing wiring. On the other hand, the multi-chip module has a benefit that it facilitates the implementation of a single module having desired functions by integrating a plurality of chips having different functions.
A description will now be given of a conventional method of manufacturing an electronic component package including at least one chip and a plurality of external connecting terminals, such as a system LSI or a multi-chip module. In a typical conventional method of manufacturing an electronic component package, at least one chip is mounted on a base such as a wiring board prepared for a single electronic component package, a terminal of the chip is connected to an external connecting terminal, and the connecting portion between the terminal of the chip and the external connecting terminal is sealed. The terminal of the chip and the external connecting terminal are connected to each other by wire bonding or flip-chip, for example. In the case where flip-chip is employed, the terminal of the chip and the external connecting terminal are connected to each other through wiring inside the wiring board. Wiring among chips in the multi-chip module is also performed by wire bonding or flip-chip, for example.
JP 2001-035993A discloses a multi-chip module in which a bonding pad connected to a chip is connected to a lead that is an external connecting terminal by wire bonding. JP 2001-035993A further discloses a technique of forming inter-chip wiring and the bonding pad through a wire-forming process. According to this publication, the wire-forming process includes a film forming step, a lithography step and an etching step, for example.
JP 2001-244403A discloses a technique wherein inter-chip wiring and pads for external connection of a multi-chip module are formed through a wafer process. According to this publication, the wafer process includes a series of steps of forming an insulating layer, forming via holes, embedding plug metals, flattening, forming films by sputtering, and forming a wiring pattern through photolithography techniques.
U.S. Pat. No. 5,926,380 discloses a method of manufacturing a chip-size semiconductor package as will now be described. In this method, first, a lead frame is bonded to the top surface of a wafer in which a plurality of semiconductor chips are formed, the semiconductor chips being aligned with chip partition lines and each having a plurality of pads on the surface thereof. Next, leads of the lead frame and the pads of the semiconductor chips are connected to each other by wire bonding. Next, the top surfaces of the leads closer to the base ends are exposed and the top and bottom surfaces of the wafer are molded. Next, conductive metallic plating is performed on the exposed top surfaces of the leads closer to the base ends. Next, the wafer and the lead frame are cut to complete the semiconductor packages.
In the typical conventional method of manufacturing an electronic component package, a series of steps, such as mounting of at least one chip on the base, connection of the terminals of the chip to external connecting terminals, and sealing of the connecting portions between the terminals of the chip and the external connecting terminals, are performed for each electronic component package. This typical method has a disadvantage that it is difficult to mass-produce electronic component packages at low costs in a short period of time.
The method of manufacturing a chip-size semiconductor package disclosed in U.S. Pat. No. 5,926,380 makes it possible to mass-produce chip-size semiconductor packages at low costs. In this method, however, to alter the specifications of semiconductor chips, it is required to start with design of a wafer including a plurality of semiconductor chips. Therefore, the method has a disadvantage that it is difficult to respond to alterations to the specifications flexibly and quickly. In addition, it is impossible to manufacture multi-chip modules through this method.
A method of manufacturing a layered electronic component package as described below is disclosed by Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999. In this manufacturing method, first, a plurality of circuits each including one or more chips are formed on a single wafer to fabricate a structure called “Neo-wafer”. Next, the Neo-wafer is diced so that the plurality of circuits are separated from each other to thereby form a plurality of structures each of which is called “Neo-die”. Next, a plurality of Neo-dice are laminated into a stack, and a plurality of stacks are laminated to fabricate an aggregate of the stacks. Next, a plurality of buses are formed on two sides of each of the stacks that the aggregate includes. Next, the individual stacks are separated. Each of the individual stacks thus formed is an electronic component package.
The above-described manufacturing method enables mass production of layered electronic component packages capable of achieving higher integration. However, this method has a disadvantage that it requires a large number of steps including a series of steps of laminating a plurality of stacks each made up of a number of Neo-dice stacked to thereby fabricate the aggregate of the stacks, forming a plurality of buses for the stacks in the state of aggregate, and then separating the individual stacks. The method has another disadvantage that, since a plurality of buses are to be formed for the stacks in the state of aggregate that is formed by laminating a plurality of stacks, it is required to precisely align the plurality of stacks that the aggregate includes, but it is difficult to perform this alignment with high precision.